A study of 3 nm CFET middle-of-the-line contact layer OCD measurement sensitivity

In advanced integrated circuit manufacturing technology, the introduction of nanosheet, forksheet, and Complementary Field Effect Transistor (CFET) architectures has created very complicated and dense vertical structures with dimensions as small as several nanometers and with many metallic layers which are not transparent to most optical wavelengths, posing a serious challenge to the metrology. We have provided a scatterometry study on a test pattern design based on the 3 nm logic design rules. Through a simulation study on typical dimensions, we have investigated various linewidths and contact depth with an algorithm based on the Rigorous Coupled Wave Analysis (RCWA).