An Efficient Hierarchical-Reduction Architecture for Aggregation in Route Travel Time Estimation

Route travel time estimation (RTTE) is crucial in intelligent transportation systems. Performing aggregation is a fundamental operation in RTTE and is widely used in the traffic prediction and route calculation stages. Observations have revealed that aggregation operations in RTTE are influenced by the road network structure and aggregation requests, resulting in irregular data access, redundant processing, and workload imbalance. Existing architectures have not addressed these issues effectively. In this study, we begin by characterizing the execution pattern of performing aggregation operations on an Intel Core CPU. Guided by these characterizations, we propose an aggregation accelerator that utilizes a hierarchical reduction architecture (HRA) to perform aggregations in RTTE efficiently. Specifically, we construct an inverted table based on the road network and aggregation requests. Building upon the concept of hierarchical reduction, we design an HRA to accelerate aggregation operations which reduces irregular data access and eliminates redundant processing. Additionally, we introduce a reconfiguration mode for HRA to mitigate workload imbalance issues. Compared to a benchmark method executed on an Intel Core CPU, our design achieves an average $10\times$ speedup.