A Capacitively Coupled Digital Isolator Using Multiple-pulse-coding Architecture with CMTI of 200 kV/s and Static Current of 60 A

This paper presents a capacitively coupled digital isolator with low power consumption and superior Common Mode Transient Immunity (CMTI). It proposes a multiple-pulse-coding architecture and a receiver with an adaptive architecture, which improve the transmission accuracy, eliminate the CMT and achieve low power consumption. The multiplepulse-coding characterizes edge signal with multi-pulses. The receiver consists of an adaptive pre-amplifier and an adaptive comparator. Fabricated in a 0.18 mu m CMOS process, the chip achieves 200 kV/ mu s CMTI, 60 mu A static current, 250 mu A dynamic current and 14 kV isolation breakdown voltage with the area of the isolation capacitance of 2 x 10(4) mu m(2).