Study of DC and Analog/RF Performances Analysis of Short Channel Surrounded Gate Junctionless Graded Channel Gate Stack MOSFET

In order to pave the path for miniaturization process, surrounded gate junctionless graded channel gate stack (SJLGCGS) MOSFET is reported in this present work, in the view of suppressing short channel effects and enhancing the DC, analog/RF performances. Gate stacking technology improves the leakage current, resulted due to down scaling of gate oxide. The emerging structure has the advantage of dropping down DIBL, reducing the subthreshold slope, minimizing threshold voltage roll-off (V th roll-off), improving the transconconductance generation factor, intrinsic gain, unity current gain frequency (f T ), Gain Bandwidth product. Hence, a thorough investigation of SJLGCGS MOSFET is invariably required to provide insight into the device performance with respect to the change in its geometrical parameters prior subjecting to fabrication to achieve reliability and dependability. In this present work, the DC performance and the analog/radio frequency performance of SJLGCGS MOSFET are studied as per the variation in length of channel (L G ), thickness of high permeability (K) gate stacking oxide (T oxh ). Linearity is a vital aspect to be considered while engaging the advanced MOSFETs for RF applications. Some linearity parameters such as third order transconductance (G m3 ), 1-dBcompression point are extracted to ensure the novelty of the device as a potential candidate for high frequency applications. The performance indexes of the device are noticeably altered with the variation in thickness of gate stacking oxide and results obtained must be taken into account for designing of analog mixed signal circuits and RFICs.