Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs

Multi-dies stack 3D-ICs are an extension of traditional 2-dies 3D-ICs to address the memory wall and footprint problems. This paper presents a complete Place-and-Route (PnR) flow to enable 3-dies stacked 3D-ICs from netlist partitioning to timing analysis, including original cross-dies co-optimization steps. The proposed flow is based on Integrity (TM) 3D-IC tool from Cadence. To demonstrate the flow, openPITON-T1 Tile design with IMEC N2 Process Design Kit (PDK) is used. The same design is implemented in normal 2D PnR flow and the proposed 3-dies stack flow. Our results show that a 3-dies stack design can achieve up to 11.4% increase in effective frequency and 50% less system footprint when compared with its 2D counterpart.