Design of an Energy Efficient Serial Communication Device using FPGA

Communication protocols play a key role in establishing communication between the devices. The communication protocols are designed in discrete ways based on framework prerequisites in the system. Serial communication is one of the widely used form of communications. In this transmission, only one bit is sent at a time. Therefore, it needs a limited number of input-output lines, that reduces the cost of the entire embedded system. Hence, it can transmit over a long distance with less bandwidth, in contrary with parallel communication, in which whole bits are sent on entire interface with few parallel channels. In this paper, an energy efficient serial communication device Universal Asynchronous Receiver Transmitter (UART) is designed. The UART design is implemented using Vivado 2020.1 and Vitis IDE tools to successfully achieve data transmission and data reception at the baud rate of 115200 Mbps. After execution, the UART design is being compared among different 7-series FPGA families on the basis of hardware utilization and total power consumed by each board respectively. The comparative analysis of different 7-series FPGA families including Kintex, Artix and Genesys2 have been done to find out the most energy efficient family.