HW/SW Co-Design of TFHE Homomorphic OR Gate via NTT-based Polynomial Multiplication on a programmable SoC

Secure computing is possible with fully homomor-phic encryption (FHE) schemes. However, such schemes re-quire computationally heavy and memory intensive operations. Hardware acceleration of their arithmetic operations is required to perform the encrypted computation within a shorter and reasonable time for the application. In this work, we address this challenge and present an FHE-specific System-on-Chip (SoC) de-sign with HW/SW co-design methodology for homomorphic OR gate of Torus Fully Homomorphic Encryption (TFHE) library, which is one of the open-source FHE library in the literature. TFHE utilizes fast fourier transform (FFT) and it mainly involves floating point calculations. We integrate the Number Theoretic Transform (NTT) based polynomial multiplication into the TFHE in order to use integer-based arithmetic. We conducted several experiments with SW and HW implementations on a pro-grammable SoC platform, a Zynq-based ZedBoard development board. Compared to the pure SW implementation, our NTT-based HW accelerator for homomorphic OR gate yielded better results in terms of computation time.