Research and Implementation of Cycle Control Technology for Time Sensitive Networking

Time Sensitive Networking (TSN) is a deterministic network technology with wide application prospects. As a part of TSN, the function of cycle control is to keep the beginning time of the scheduling period of each switch node in the TSN network synchronized, which is the premise of implementing the TSN Time Aware Shaper (TAS). The IEEE 802.1Qbv specification describes the principle of cycle control, but there is a lack of relevant research on how to implement high-precision cycle control in TSN switch devices. In this paper, an accurate cycle control method called Cycle Synchronization Algorithm (CSA) is proposed. The algorithm generates a beginning signal (cycle_start) for each cycle on the basis of Precision Time Protocol (PTP). The paper proves that the cycle synchronization deviation is not greater than the PTP clock synchronization deviation. In a six-node TSN network based on a FPGA array, the effectiveness and stability of the CSA algorithm is verified.