The Effect of $\text{CdSe}_{\mathrm{X}}\text{Te}_{1-\mathrm{X}}$ Thickness on the $\text{CdSe}_{\mathrm{X}}\text{Te}_{1-}$ x/CdTe Solar Cell Performance

The effect of the CdSe _X Te _1-X (CST) thickness on the performance of CdSe _X Te _1-X /CdTe solar cells at different Se (x) compositions and annealed at various CdCl ₂ temperatures has been studied. The cell configuration was superstrate as ITO/MZO/CdSe _x Te _1-X /CdTe/Back Contact. Both CST and CdTe were deposited by the close-spaced sublimation (CSS) process. The CST thickness and Se composition varied from 0.25-1 μm and 6-29% respectively. The open circuit voltage (V _OC ) was found to decrease with increasing CST thickness and Se composition. V _{OC decreases, and JSC increases due to the decrease in the bandgap of CST. A CST thickness of 0.50 μm produced the optimum VOC and fill factor, thus giving the optimum efficiency. Also, 430°C CdCl2 annealing temperature appears to result in a higher minority carrier lifetime, which is responsible for the improved cell performance observed for devices annealed at this temperature.}