A 10-bit 1MSPS SAR Quantizer with Differential Charge Compensation for 2Vp-p Signal Range

A low power successive approximation register (SAR) quantizer with differential charge compensation is presented. Asynchronous logic and top-plate sampling are adopted to achieve a low-power design. A differential charge compensation technique is proposed to eliminate the intrinsic signal range loss introduced by the top-plate sampling. The presented SAR quantizer outputs 10-bit digital results by 1MS/s under the power supply of 1.2V, consuming 35uW. The post-simulation results show the signal range is full as 2Vp-p and peak SNDR of 60.11dB, resulting in a figure of merit (FoM) of 42 fJ/conversion-step. This design is using 180-nm CMOS technology and the core area is about 0.0944mm ² .