A 0.53ns Delay Floating-voltage Level Shifter with Ultra-high dV/dt Immunity for GaN FETs Gate Driver Application

A sub-nanosecond delay floating voltage Level Shifter (LS) with ultra high dV/dt immunity is presented in this paper. Based on pulse-triggered architecture, the proposed level shifter adopts Common Current Canceller (CMCC) and Auxiliary Pull-up Circuit (APUC). The dV/dt immunity reaches 250V/ns and V GS overshoot of pull-up PMOS is limited. Simulation results based on 0.18μm BCD process suggest that the propagation delay is 0.53ns and ET is 407pJ typically, with V SW =30V. The FOM is 28.02 (pJ×ns)/(μm ³ ×V).