Research and Design of RISC-V Four-Stage Out-of-Order Execution Processor

2022 IEEE 16th International Conference on Solid-State &amp Integrated Circuit Technology (ICSICT)（2022）

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2-3 stage pipelines,32-bit low-power high-performance processor,designed Dhrystone,embedded processors,four-stage pipeline architecture,four-stage pipeline structure,instruction prediction,open-source processor cores,open-source RISC-V instruction set,performance evaluation,RISC-V basic integer operations,RISC-V four-stage out-of-order execution processor,sequential execution,sequential launch,small-scale processors

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