Ultra-Low Power 2.4 GHz Receiver Design Techniques for IoT Applications
2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)（2022）
摘要
This paper presents ultra-low power completely on-chip radio frequency (RF) receiver design techniques for high-speed Internet-of-Things (IoT) applications using TSMC 40nm CMOS process. Two RF receivers are designed to present the advantages of coherent and non-coherent detection in the receiver path. The proposed non-coherent detection receiver (Rx I) utilizes a novel pseudo-balun envelope detector and a comparator to decode on-off keying (OOK) modulated signal at a 200-kbps data rate in the 2.4 GHz ISM band. The simulated results show that the receiver can achieve -52 dBm sensitivity for only 13.3 nW of power consumption from 0.8/0.5 V supply. The proposed coherent detection receiver (Rx II) utilizes a mixer-first low intermediate frequency (IF) receiver architecture with an in-built frequency synthesizer to decode OOK modulated signal at a 5 Mbps data rate in the 2.4 GHz ISM band. The simulated results show that the receiver can achieve -80 dBm sensitivity for only 105 μW of power consumption from a 0.9/1 V supply.
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关键词
bit rate 200 kbit/s,bit rate 5 Mbit/s,coherent detection,coherent detection receiver,comparator,frequency 2.4 GHz,high-speed Internet-of-Things applications,in-built frequency synthesizer,IoT applications,keying modulated signal,mixer-first low intermediate frequency receiver architecture,noncoherent detection receiver,on-chip radio frequency receiver design techniques,on-off keying modulated signal,OOK modulated signal,power 105.0 muW,power 13.3 nW,power consumption,pseudobalun envelope detector,receiver architecture,receiver path,RF receivers,size 40.0 nm,TSMC 40nm CMOS process,ultra-low power 2.4 GHz receiver design techniques,voltage 0.5 V,voltage 0.8 V,voltage 0.9 V,voltage 1.0 V
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