Hierarchical bonding yield test structure for flexible high channel-count neural probes interfacing asic chips

This study presents novel, hierarchical bonding yield test structures designed to establish and validate a high-density interfacing process between CMOS ASIC chips and highly flexible neural probes made of polyimide. The efficient test procedure allows to identify open circuits within the nxn bonding pad array in order to locate electrical defects between contact pairs using a minimal number of electrical measurements. Applying flip-chip bonding to interface PI-based test structures with electroplated pads and silicon dummy chips mimicking neural probes and ASIC chips, respectively, a bonding yield of 97.2 % has been achieved.