Single-scan Run Length Algorithm for Real-time Fiducial Marker Detection Based on FPGA Devices.

Image processing pipelines involved in detecting markers from real-time video employ contour detection algorithms. Field Programmable Gate Arrays (FPGA) can provide greater computing power due to parallel processing and pipelining of the different stages in these algorithms. However, FPGA implementation of different contour detection methods remains challenging due to resource limitation and timing constraints. In this work a novel approach for a complete pipeline has been presented based on FPGA. The method used for the detection of fiducial markers from real-time video streams is based on a single-scan approach. Implementation of such pipeline into reconfigurable technology is specially challenging compared to software-oriented implementation as pointers, dynamic structures, efficient use of resources, etc. need to be considered. A driver is the need to fit the design into low-cost reconfigurable devices. To help face the related challenges of a hardware implementation High Level Synthesis (HLS) technology has been adopted, which implies reengineering of the reference algorithms. The results show a successful detection of markers over a dataset acquired in a controlled indoor environment with different resolutions at different distances. The proposal has been prototyped and tested on a Zedboard with Xilinx Zynq®-7000 SoC.