A memory allocation method for MPU memory protection unit
2023 IEEE International Conference on Control, Electronics and Computer Technology (ICCECT)(2023)
Abstract
At present, the Memory Protection Unit (MPU) of Cortex-M series processors needs to align the address with the rule of 2
n
when protecting the memory, but this method will cause memory waste in multi-task memory allocation. Therefore, this paper proposes a method that uses multiple MPU protected regions to concatenate and superimpose to protect a region simultaneously, which effectively reduces the memory waste caused by alignment. The experimental results show that, compared with using a single MPU protected region, using four regions for concatenation and superposition can reduce the memory waste by 63%, and effectively improve the memory utilization.
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Key words
Cortex-M,memory protection unit,memory waste,overlaying of memory protected area
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