Low-power high-dynamic-range analog front-end for picosecond waveform sampling ASICs

This short communication presents an analog front-end (AFE) circuit used in the switched-capacitor array (SCA) for the waveform sampling ASIC. The idea to use in SCA-AFE native transistors which are common in today’s CMOS technologies offers a feasible solution to the issue of achieving picosecond time resolution with a low supply voltage. The circuit features a MOS capacitor and a source follower both of which are implemented with the native transistors, and a simple rail-to-rail comparator. A prototype PISTWAVE1 ASIC is designed in a 55 nm CMOS with a single 1.2 V supply voltage, the experimental results show the ASIC achieves a dynamic range of 0.1∼1.1 V, a 65.3 dB signal-to-noise ratio (SNR) with voltage calibration and a less than 10 ps time resolution. The overall power consumption is less than 10 mW/channel at a sampling rate of nearly 6 GS/s.