Converging-guiding-track design enables 100% growth deployment rate of ultrathin monocrystalline silicon nanowire channels

A low temperature catalytic growth of orderly ultrathin silicon nanowires (SiNWs) is desirable for the construction of monolithic 3D stacked electronics but usually suffers a large diameter fluctuation and a low growth deployment rate (GDR). In this work, the ultra-confined growth dynamics of in-plane solid-liquid-solid SiNWs within narrow groove tracks has been systematically investigated, and a converging-guiding-track strategy is proposed and testified to accomplish 100% GDR of ultra-dense and uniform SiNW array, with diameter and spacing of only D-nw = 22.5 +/- 3.5 nm and 25 nm, respectively. Despite a low temperature growth at 350 degrees C, the SiNWs are found to be all monocrystalline and Si?100? oriented, while prototype Schottky barrier tunneling field effect transistors built on the SiNW channels demonstrate a high I-on/off ratio and subthreshold swing of >10(5) and 197 mV dec(-1). This new strategy complements a long-missing key capability of catalytic growth approach to serve a reliable integration technology of ultrafine high quality 1D c-Si channels, without the need of preexisting wafer substrate, for a wide range of 3D electronics, neuromorphic, and logic-in-memory functionalities.