A Low-Cost Combinational Approximate Multiplier

This document provides instructions for the design of a purely combinational, multiplexer-based, low-cost multiplier, for machine learning multiplications. The main idea of the algorithm is to remove the most significant bits. Starting from the most significant 1 and after finishing the main multiplication, add back the number of ignored right-hand bits. The main intention of this design is area and power reduction. Since it’s an all-combinational circuit its critical path’s delay is one clock cycle of the main module that it’s going to be used in.