Securing a RISC-V architecture: A dynamic approach

S. Pillement,M. Mendez Real, J. Pottier, T. Nieddu, B. Le Gal,S. Faucou, J. L. Bechennec, M. Briday,S. Girbal,J. Le Rhun, O. Gilles,D. Gracia Perez, A. Sintzoff, J. R. Coulon

2023 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE（2023）

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摘要

The SecureV (also known as SecV) project offers an innovative, open-source hardware, secure, and high-performance processor core based on the RISC-V ISA. The originality of the approach lies in the integration of a complete solution to increase security based on dynamic code transformation, covering 4 of the 5 NIST1 functions of cybersecurity via monitoring (identify, detect), obfuscation (protect), and dynamic adaptation (react).

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关键词

Cybersecurity,RISC-V,open-source hardware

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