Impact of Trapped Charge Vertical Loss and Lateral Migration on Lifetime Estimation of 3-D NAND Flash Memories

In this work, a fundamental problem of the conventional temperature-accelerated life-test methodology is revealed owing to the coexistence of three failure mechanisms in 3-D NAND Flash memories. Different from previous studies, for the first time, we are able to separate the roles of trapped electron vertical loss and lateral migration experimentally in multiple bake temperature and different program/erase (P/E) cycle number without any simulation tool and fitting model according to the neighboring data pattern effect on threshold voltage $\boldsymbol{(\mathrm{V}_{\mathrm{t}})}$ traces and the extracted activation energies $\boldsymbol{(\mathrm{E}_{\mathrm{a}})}$ under various conditions. We found that Vt retention loss at lower temperatures tends to be dominated by trapped electron direct tunneling (DT) out from silicon nitride (SiN) to Si channel. At bake temperature rises, Vt loss in non-cycled cells is gradually originated from SiN trapped electron lateral migration via thermally assisted tunneling (ThAT) while Vt loss in P/E-stressed devices is mainly caused by trapped electron vertical escape from SiN storage layer through Frenkel-Poole (F-P) emission and the subsequent positive charge-assisted tunneling (PCAT) process.