3.2Tb/s Heterogeneous Photonic Integrated Circuit Chip in a Co-Packaged Optics Configuration

Damien Lambert,Jeff Rahn,Majid Sodagar,Murtaza Askari,Paveen Apiratikul,John Spann,Thang Pham,Yishen Huang,Stephen Krasulick

OFC（2023）

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摘要

We present a low-cost, scalable 3.2Tbps heterogenous photonic integrated circuit chip assembled in a co-packaged optics configuration. The integration of III-V material directly into the Silicon-Photonic chip offers clear form-factor, density, and thermal dissipation advantages.

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关键词

3.2Tbps heterogenous photonic integrated circuit chip,bit rate 3.2 Tbit/s,copackaged optics configuration,density,form-factor,III-V material,silicon-photonic chip,thermal dissipation

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