A 7GHz ERBW 1.1GS/s 6-bit PVT Tolerant Asynchronous CI-SAR with only 8.5fF Input Capacitance

Jongho Kim, Gyuchan Cho,Jintae Kim

CICC(2023)

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摘要
SAR ADC has been widely used as a slice ADC in time-interleaved ADCs (TlADCs) due to its fast conversion speed, superior energy efficiency, and scaling-friendly nature. While the flash-assisted SAR [1] or the pipelined SAR [2] can boost the conversion speed beyond 1GS/s, extra input loading from the dual path input [1] and the area penalty of having multi-stages [2] hinder increasing the interleaving factor when used as a slice ADC. One alternative that recently emerged is the charge injection SAR (ci-SAR) ADC [3], featuring compact size owing to its CDAC-less structure. However, conventional ci-SAR suffers from three challenges: 1) The charge injection cells (ClCs), when activated, create large current pulses, requiring oversized input sampling capacitance ($\mathrm{C}_{\mathrm{i}\mathrm{n}\mathrm{t}}$) that demerits the area efficiency. For instance, $\mathrm{C}_{\mathrm{i}\mathrm{n}\mathrm{t}}$ in [3] is 200fF, which is unnecessarily large considering the kT/C noise of 6-bit resolution. 2) The input full scale varies significantly depending on the PVT condition, resulting in the performance degradation. As shown in Fig. 1, this is attributed to the dependency of injection current ($1_{\mathrm{t}\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{s}\mathrm{f}\mathrm{e}\mathrm{r}}$) on the overdrive voltage of transfer devices ($\mathrm{M}_{1,2}$) and the pulse width of the transfer pulse ($\mathrm{T}_{\mathrm{t}\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{s}\mathrm{f}\mathrm{e}\mathrm{r}}$), both of which are function of process, temperature, and supply voltage. 3) The monotonic switching inherent in CIC-DAC makes the comparator vulnerable to input common-mode ($\mathrm{V}_{\mathrm{l}\mathrm{N}\mathrm{C}\mathrm{M}}$) dependent dynamic offset, potentially degrading the overall linearity. One recently published ci-SAR ADC in [4] tried to reduce the area penalty by sharing the ClC-DACs at the expense of slow conversion rate of 0. 75GS/s per slice, but the PVT-sensitivity and the dynamic offset issues are still unresolved.
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6-bit PVT tolerant asynchronous CI-SAR,6-bit resolution,75GS,8.5fF input capacitance,area efficiency,area penalty,capacitance 200.0 fF,capacitance 8.5 fF,charge injection cells,charge injection SAR ADC,conventional ci-SAR suffers,dual path input,extra input loading,fast conversion speed,flash-assisted SAR [1],frequency 7.0 GHz,injection current,input common-mode,input full scale varies,interleaving factor,oversized input sampling capacitance,pipelined SAR,recently published ci-SAR ADC,scaling-friendly nature,slice ADC,superior energy efficiency,time-interleaved ADCs,transfer pulse
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