Vertical GaN Transistor with Semi-Insulating Channel

herein, vertical GaN transistors with a semi-insulating (SI) 1.3 mu m thick channel layer and C doping of 1 x 10(17) cm(-3) are studied. Structures are grown using a metal-organic chemical vapor deposition on conductive GaN substrates. SI GaN is sandwiched between 2.5 mu m thick n-GaN drift layer (Si doping of approximate to 1 x 10(17) cm(-3)) and a top n-GaN contact layer. A circular mesa region with a diameter of 180 mu m is patterned using a deep dry etching. The gate contact formed on the mesa sidewall is insulated from the vertical channel using a 20 nm thick Al2O3 grown by an atomic layer deposition. Despite a robust layout, transistors transfer characteristics indicate normally off behavior if extracted from the linearly scaled current-voltage characteristics and an open channel drain current of 30 mA at the gate bias of 4 V. Achieved on/off ratio is 10(7) at -2 V subthreshold gate bias when the full channel depletion is reached. And, 200 ns long gate pulse characteristics show only a marginal trapping even though no post-metallization annealing is performed. By comparing experimental results with modeling, mobility of free electrons in the channel is found to be about 45 cm(2) V-1 s(-1).