16.7 A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications

Giuseppe Desoli,Nitin Chawla,Thomas Boesch,Manui Avodhyawasi,Harsh Rawat,Hitesh Chawla,VS Abhijith,Paolo Zambotti,Akhilesh Sharma,Carmine Cappetta,Michele Rossi,Antonio De Vita,Francesca Girardi

2023 IEEE International Solid-State Circuits Conference (ISSCC)（2023）

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Key words

accumulation resolution loss,analog IMC,analog SRAM IMC solutions,capacitive sharing techniques,compute-intensive data-driven AI workloads,computing inaccuracy,deep-learning edge applications,device variations,digital IMC,digital logic,digital SRAM IMC,dynamic range,edge AI,emerging memory technologies,end-to-end system-level energy efficiency,FD-SOI,general-purpose workloads,IMC tiles,In-Memory Computing MultiTiled NN Accelerator,integrated computing device,logic bit cells,low memory density,low-cost testing,neural processing systems,Neural Processing Unit,pushed technology scaling rules,resistive sharing techniques,row parallelism,scalable design time parametric NPU,size 18.0 nm,system level,system scalability

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