A 5.4-Gb/s, 0.57-pJ/bit, Single-Loop Referenceless CDR With an Unlimited Bilateral Frequency Detection Scheme

This article proposes a single-loop referenceless clock and data recovery (CDR) with a bilateral bang-bang phase and frequency detector (BBPFD). The CDR achieves an unlimited frequency acquisition range in both directions of the lock frequency. The proposed BBPFD tracks the frequency by using the asymmetry of UP/DN output probability of the bang-bang phase detector (BBPD). A seamless transition between frequency acquisition and phase tracking is possible through a simple modification of the existing BBPD. The CDR has a locking time of $3 \mu \text{s}$ under the PRBS7 pattern. The test chip was fabricated in a 28-nm CMOS process. It supports a 5.4-Gb/s link rate, making it compatible with the embedded DisplayPort (eDP) standard v1.2. The total power consumption is 3.04 mW at a speed of 5.4 Gb/s/lane. The power efficiency is 0.57-pJ/bit at a supply voltage of 0.9 V.