32-Bit Non-pipelined Processor Realization Using Cadence

In modern electronics field, power constraint is emphasizing factor, since most of electronic devices are handheld. With the advent of IoT, processors design with high performance, low power dissipation is of primary concern. In this work, a 32-bit non-pipelined processor is implemented using Cadence tool of 0.35 µm technology library with minimal working units along with optimal performance. Static power, net power, dynamic power for the proposed design are obtained in nano-watts. Basic building blocks of the design include the CPU along with memory controller. The data size is 32-bit, and address size is 16-bit. Four-bit operational code is employed. Nine instructions are used in the design. Four-bit bidirectional IO is implemented. Memory is divided for ROM and RAM input–output ports. Design avail clock frequency of 80 MHz. RTL simulation is done along with synthesis, place and route, and LVS and DRC rule check. For the work implemented, no of cells of CPU are 1127, memory controller are 2071, the total leakage power is 4.38 nW, dynamic power is 56436431.19 nW, short-circuit power is 41474454.01 nW, and net power is 14960177.18 nW.