FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System

Through-Silicon-Via (TSV) is expected to realize high-performance, low-power consumption, and low-cost 3D-LSI (Large Scale Integration) system. It is realized by integrating pre-manufactured chips with a 3D Standard Chip Stacking System (3D-SCSS) through a standard bus TSV connection. However, it is difficult to define a standard chip connection mechanism. This paper proposes an FPGA emulation of the TSV dataflow network for evaluating the performance of 3D-SCSS. To emulate 3D-SCSS, multiple-clock domains are assumed to overcome the problem of jitter in the global clock, which is a separated clock domain model. Simple dataflow experiments are done where processes are deployed to different chips and communicate among the chips in the 3D-SCSS. The evaluation shows that the emulation method is suitable to measure the latency performance of the proposed TSV dataflow network.