A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration

Ring amplifiers (ringamps) have been shown to improve pipelined ADC performance by relaxing the traditional bottleneck imposed by power-hungry class-A residue amplifiers $[1,2]$. However, the operation of several high-performance ringamp structures is heavily dependent on device parameters and supply voltage, and thus, often sensitive to PVT variation. This creates challenges for applications in extreme environments, such as cryogenic quantum computing, space, and automotive. To overcome this issue, this work introduces a PVT-robust ringamp with pole-aware bias calibration and a biasenhancement technique. Furthermore, to deal with insufficient gain in advanced CMOS, we also propose a cascode Correlated Level Shifting (cascode-CLS) technique. These three techniques enable a prototype 12b 250MS/s pipelined ADC that achieves SNDR higher than $55 \mathrm{~dB}$ across $4.6 \mathrm{~K}$ to $400 \mathrm{~K}$ operating temperature range without requiring gain calibration. To the best of our knowledge, this work is the first pipelined ADC reported to operate at less than $40 \mathrm{~K}$.