DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC

As computation-in-memory (C1M) architecture is a prominent solution for energy efficiency in Al edge devices, designing a robust, accurate, and dense C1M architecture has become essential. Capacitor-based C1M has been widely adopted thanks to the high linearity of the capacitors. Fig. 1 explains various challenges and motivations of C1M with the proposed C1M architecture. The first challenge is to implement linear multi-bit computing. A multiply-and accumulation (MAC) value with different input and weight combinations shows different analog MAC voltages, degrading accuracy. Bit-parallel is an alternate solution for realizing multi-bit computing [1]. However, it shows significant power and area overheads because of multiple analog-to-digital converters (ADCs) and shift-and-adders for one MAC operation. Another challenge is ADC dynamic range utilization. Because the analog MAC dynamic range depends on neural-network, it is smaller than ADC dynamic range. This dynamic range mismatch degenerates the resolution with the same ADC bit-width. The last challenge is the area overhead of the ADC, which requires the ADC to be shared. The ADC shared with N columns degrades throughput by 1/N and requires Opamps to keep the analog MAC voltages from non-selected columns. To address the above issues, this paper proposes: (i) Capacitive coupling-based weighted-capacitor SRAM C1M (WC-CIM) with linear multi-bit computing, (ii) ADC dynamic range calibration (DRC) to improve resolution and minimize wasted dynamic range, and (iii) A novel capacitive-DAC (cap-DAC) driver with shared successive approximation (SAR) logic [2] for compact ADC.