Design of Quasi Delay Insensitive Combinational Circuits Based on Optimized DIMS

While the clock signal is challenging in synchronous circuit design, asynchronous circuits are promising as they eliminate such a signal. An essential class of asynchronous circuits due to simplified timing analysis and being robust to PVT variations (process, supply voltage, temperature) is called Quasi Delay Insensitive (QDI). However, QDI circuits have high hardware increases due to signal coding, which uses delay-insensitive code. This paper proposes extensions to methods called NCL_D and RC that are based on the DIMS style and synthesize QDI combinatorial circuits. These extensions propose three optimized DIMS styles aimed at hardware reduction. The extensions proved promising for a set of eight examples compared with the NCL_D and RC methods. Our proposal obtained an average reduction of up to 51.4% in the estimated number of transistors.