A 41-nW SAR ADC with a FIA-based Comparator and a Bulk-driven Latch for ECG Applications

This paper presents several innovative low power techniques to design an ultra-low power SAR ADC for ECG application. Body driven (BD) or biasing (BB) techniques are used in bootstrapped switches and SAR logic to minimize leakage power consumption. In addition, we propose a dynamic comparator with a floating inverter amplifier (FIA) architecture with a modified strong-arm latch and a BD input stage to reduce the noise and offset by reducing the noise current and eliminating the influence of common-mode input voltage. Lastly, the VCM based switching scheme allows a fixed common-mode input voltage swing, relaxing the offset requirement of dynamic comparator. The proposed SAR ADC is implemented in a 180nm CMOS process. The whole ADC consumes 41nW at a sampling rate of 10kS/s under a supply of 0.6V, obtaining the ENOB of about 10bit and resolution of 10bit.