An in-depth investigation of gate leakage current degradation mechanisms in 1.2 kV 4H-SiC power MOSFETs

In this paper, a comprehensive study on the forward and reverse current degradation mechanisms in 1.2 kV planar SiC MOSFETs are investigated. With the help of Sentaurus TCAD simulations, numerical fitting method, step-bias stress, current-voltage (I-V) and capacitance-voltage (CV) experiments, we proposed defect-related transport models to describe the progression of gate leakage currents under forward and reverse high biases. It is found that, (1) trap-assisted tunneling (TAT) and Fowler-Nordheim (FN) tunneling dominate the forward low and high current transport process respectively. Moreover, the holes trapping is mainly responsible for the degradation of gate oxide and premature breakdown of SiC MOSFETs; (2) the reverse leakage current under high electric field is mainly carried by FN tunneling electrons, which lead to an increase of the intermediate localized states distributed in the SiC/SiO2 interface.