A Low-Power Approximate Multiplier with Sign-Focus Compressor and Error Compensation

Approximate computing is an emerging and effective means of reducing energy consumption in digital circuits, which is critical for improving the energy efficiency of edge computing devices. In this paper, we propose a novel low power signed approximate multiplier based on a sign-focus compressor and error compensation. The sign-focus compressor is a compressor customized for partial product matrix of signed operands. After probabilistic analysis, it is reduced to the simplest logic circuit. At the same time, we truncate the low N-I columns of the partial product matrix and perform error compensation. By logic synthesis evaluation, the proposed approximate multiplier saves 49.84% power, 46.41% area and 24.65% delay compared to the exact multiplier. Compared with other state-of-the-art approximate multipliers, the proposed approximate multiplier has better accuracy-performance trade-off.