An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips

Vision chip is a high-speed image processing device, featuring a massively-parallel pixel-level processing element (PE) array to boost pixel processing speed. However, the collocated processing unit and fine-grained data memory unit inside each PE impose a huge requirement on memory access bandwidth as well as big area and energy consumption. To overcome this bottleneck, this paper proposes a full custom $\mathbf{8T}$ SRAM-based Processing-in-memory (PIM) architecture to realize pixel-parallel array processor for high-speed energy-efficient vision chips. The proposed PIM architecture is constructed by emending multiplexer-based computing circuits into a dual port 8T SRAM array, so as to form a PIM PE array. Each PIM PE holds a 66-bit 8T SRAM cell block embedding in-memory logic functions, of which 64-bit 8T SRAM cells serving as the PE memory, 2-bit 8T SRAM cells acting as a buffer register in the PE. A full custom physical layout of a 16 $\times \boldsymbol{16}$ prototyping PIM PE array is designed and simulated using a 65 nm CMOS technology. The simulation results demonstrate that our proposed PIM PE architecture can achieve 200 MHz operation at 1.2 V, and reach a high energy efficiency of 3.97 TOPS/W while keeping a compact area of 0.129 $\mathbf{mm}^{2}$ .