An Ultra-Low Power Fast-Transient Response Capacitor-Less Low-Dropout Regulator (LDO)

In this paper, an enhanced amplifier is employed for ameliorating the general performance of low-dropout regulators. The presented LDO possesses not only current boosting at the power transistor gate, but also improved voltage regulation of the LDO due to the combination of the Flipped Voltage Followers (FVFs) adaptive input structure and local common mode feedback (LCMFB) technique. Moreover, the realization comprehensive performance improvement of the LDO demands only 2 μA quiescent current, resulting in the current efficiency is greatly improved. The designed LDO is simulated in 0.18 μm process. From simulation experiments, the undershoot is 466 mV under the load switching response of 2 μA-100 mA within 500 ns edge time. Moreover, the current efficiency in this design is up to 99.99%.