A 16 GB 1024 GB/s HBM3 DRAM with Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.

Yesin Ryu,Sung-Gi Ahn,Jae Hoon Lee,Jaewon Park,Yong Ki Kim,Hyochang Kim, Yeong Geol Song,Han-Won Cho, Sunghye Cho,Seung Ho Song,Haesuk Lee,Useung Shin,Jonghyun Ahn,Je-Min Ryu,Sukhan Lee,Kyoung-Hwan Lim,Jungyu Lee,Jeong Hoan Park,Jae-Seung Jeong,Sunghwan Joo, Dajung Cho,So Young Kim,Minsu Lee, Hyunho Kim, Minhwan Kim, Jae-San Kim,Jinah Kim, Hyun Gil Kang,Myung-Kyu Lee,Sung-Rae Kim,Young-Cheon Kwon,Young Yong Byun,Kijun Lee,Sangkil Park,Jaeyoun Youn,Myeong-O Kim,Kyomin Sohn,Sang-Joon Hwang,Jooyoung Lee

IEEE JOURNAL OF SOLID-STATE CIRCUITS（2023）

引用 13|浏览34

关键词

3-D-stacking memory,data-bus,DRAM,error check and scrub (ECS),high-bandwidth memory (HBM),memory built-in self-test (MBIST),on-die error-correcting code (OD-ECC),system reliability,availability,and serviceability (RAS)

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