Substrate noise evaluation for lightly doped 45nm N-MOSFET using physical simulation models

Analyzing substrate noise for an n-channel MOSFET (NMOS) substrate has been developed using various concepts such as virtual separation concept, p-contact to p-contact model and transistor switching noise model. A design is necessary for the substrate design development to minimize noise in FoMs (Figure Of Merits) and reduce threshold voltage developed noise. In the proposed model, a substrate-induced chip used for finding the noise in drain current has been improved with the increased doping density of an NMOS device. From a substrate noise coupling network with the proposed low signal equivalent circuit, the system measures noise at NMOS substrate using a hot carrier injection model. The proposed concept has been implemented in TCAD-SILVACO software, the design was made in ATHENA, and its corresponding electrical characteristics are simulated by the ATLAS software tool. This model extracts parameters such as overall noise in FoMs, drain current-gate current bias analysis, cross-correlation, and minimized threshold value. After capacitive coupling is achieved over different operation conditions and dimensions, excellent output is from simulated noise data.