A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1/2-Order DTC INL Calibration.Yumeng Yang,Wei Deng,Angxiao Yan,Haikun Jia, Junlong Gong,Zhihua Wang,Baoyong ChiISSCC（2023）引用 0|浏览7暂无评分AI 理解论文溯源树样例生成溯源树，研究论文发展脉络Chat Paper正在生成论文摘要
