An expandable 36‐channel neural recording ASIC with modular digital pixel design technique

Abstract This paper presents the design and implementation of an expandable neural recording ASIC for multiple‐channel neural recording applications. The ASIC consists of 36 modular digital pixels (MDPs) and a global digital controller (GDC) circuit. Each MDP has an analog frontend (AFE) circuit, a 12‐bit successive approximation register ADC (SAR ADC), and a local digital controller (LDC) circuit. It achieves 5.9‐μV input referred noise (IRN), 10.8‐effective number of bits (ENOB), 37.8‐μW power consumption, and 0.095 mm2 area per channel. The ASIC is implemented in commercial SMIC 0.18‐μm CMOS process and validated by in‐vivo experiment on a lab mouse with a 36‐channel silicon‐based neural probe.