LearnedFTL: A Learning-Based Page-Level FTL for Reducing Double Reads in Flash-Based SSDs
International Symposium on High-Performance Computer Architecture(2023)
Abstract
We present LearnedFTL, a new on-demand page-level flash translation layer
(FTL) design, which employs learned indexes to improve the address translation
efficiency of flash-based SSDs. The first of its kind, it reduces the number of
double reads induced by address translation in random read accesses. LearnedFTL
proposes three key techniques: an in-place-update linear model to build learned
indexes efficiently, a virtual PPN representation to obtain contiguous PPNs for
sorted LPNs, and a group-based allocation and model training via GC/rewrite
strategy to reduce the training overhead. By tightly integrating the
aforementioned key techniques, LearnedFTL considerably speeds up address
translation while reducing the number of flash read accesses caused by the
address translation. Our extensive experiments on a FEMU-based prototype show
that LearnedFTL can reduce up to 55.5% address translation-induced double
reads. As a result, LearnedFTL reduces the P99 tail latency by 2.9×
∼ 12.2× with an average of 5.5× and 8.2× compared to
the state-of-the-art TPFTL and LeaFTL schemes, respectively.
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