Design and Analysis of Heterojunction Inverted-T P-FinFET on 14nm Technology Node for Use in Low-Power Digital Circuits

FinFET (fin-shaped field-effect transistor) devices hold unique properties like reduced short-channel, high I on /I off (On Current/Off Current) current ratio, and improved channel control making them a possible nanoscale successor for existing CMOS (Complementary Metal Oxide Semiconductor) based devices. The delay and power play a crucial role while designing the digital circuit. A new heterojunction inverted-T shaped P-FinFETs is designed and compared to other planers PMOS (p-type metal oxide semiconductor) in terms of device parameters and CMOS-based inverter circuit performance. The proposed inverted-T P-FinFET provides higher On-current (6.61 × 10 –6 A), improved I on /I off (On Current / Off Current) current ratio (1.99 × 10 13 ), and minimum off current (3.32 × 10 – 19 A) with minimum drain induced barrier lowering (15.4 mV/V) and lower value of subthreshold swing (43.2 mV/Dec) as compared to the planer PMOS. Process variation was performed on the proposed heterojunction P-FinFET on different parameters like work function, mole fraction (x) in Silicon Germanium (Si 1-x Ge x ) material, and temperature. When the work function (Ø) varies from 2.25 to 4.36 eV, then it shows an increase of 0.64 in the I off (off current) and 0.08 in the I on (on current) of the P-FinFET. When the mole fraction value decreases from 0.5 to 0.1 it shows a 0.06 increase in the I off (off current) and a 1.77 increase in the I on (on current) of the P-FinFET. Similarly, when the temperature varies from 200 to 400 K with the step of 50 K, it decreases the threshold voltage by 0.77 which shows a lesser variation in the threshold voltage of the proposed P-FinFET. Further, low-power circuits like the inverter designed in this paper with help of heterojunction P-FinFET and N-FinFET of T-shaped fin and compared its performance parameters like noise margin, average delay, and average power with other inverter circuits. The proposed inverter shows a low state noise margin (NM L ) that is 0.38 and a minimum average delay of 0.685 ns with a lesser power consumption of 2.35 µW.