Implementation of STDP for Spintronics based SNN using 90nm CMOS Technology

Spiking Neural Network (SNN) is a sparse-driven network that can be used in low-power neuromorphic applications. Training such a network is still a challenge. In this paper, we have implemented and analyzed a biologically plausible unsupervised Spike Time Dependent Plasticity (STDP) algorithm for training SNNs. The implementation was done in 90nm CMOS Technology using Cadence Virtuoso circuit simulator. The implementation was verified using MNIST dataset for handwritten digits. The MNIST images were converted to time-dependent spike trains by rate encoding technique using the Google Colab platform. The parameter specifications were analyzed in Cadence Virtuoso. Dependency of each parameter on the circuit characteristics was obtained and simulations show that the time constant and value of the capacitor in the circuit are linearly dependent.