Technique research of embedded event receiver for BEPC-II

Purpose The event receiver is an important component of the BEPC-II timing system. It receives event codes from the event generator and then generates triggers and interrupts. The currently applied event receiver is implemented in a single FPGA board, which has to work in conjunction with a single-board computer and an external bus chassis. With the rapid development of System-on-Chip (SoC) technology, combining them in one SoC is more efficient, more integrated, and cheaper. Thereby, an embedded event receiver based on ZYNQ SoC is proposed. Methods and Results In this paper, some key techniques of embedded event receiver have been researched. These techniques have been implemented in an embedded event receiver prototype named ER-Z. And the function test results show that ER-Z has the ability to receive event codes and handle them through interrupts while attaching timestamps with event clock precision. The performance test results show that the average interrupt latency is less than 30 μs and the average AXI-Lite read latency is less than 170 ns.