Electrical Simulation on Silicon Nanowire Field-effect Transistor Biosensor at Different Substrate-gate Voltage Bias Conditions for Charge Detection

In this work, the impact of different substrate-gate voltage bias conditions (below and above the device threshold voltage) on current-voltage characteristics and sensitivity of a silicon nanowire field-effect transistor (SiNW-FET) biosensor was investigated. A 3-dimensional device structure with n-type SiNW channel and a substrate gate electrode was designed and electrically simulated In the Silvaco ATLAS. Next, the SiNW channel was covered with a range of interface charge density to mimic the charged target biomolecule captured by the device. The outcome was translated into a drain current versus interface charge semi-log graph and the device sensitivity was calculated using the linear regression curve's slope of the plotted data. The device's electrical characteristic shown higher generation of output drain current values with the increase of negative substrate-gate voltage bias due to the hole carriers' accumulation that forms a conduction channel in the SiNW. Application of higher negative interface charge density increased the change in drain current, with the device biased with higher substrate-gate voltage shows more significant change in drain current. The device sensitivity increased when biased with higher substrate-gate voltage with highest sensitivity is 75.12 nA/dec at substrate-gate voltage bias of -1.00 V.