A Mathematical Analysis of Wire Resistance Problem in Memristor Crossbars

Memristor crossbars represent promising candidates for accelerating linear algebra computation. The array architecture enables strong parallel computational properties and support data storage for reducing the energy consumption due to data migration. Despite their great application in machine learning algorithms for training neural networks, the resistance of metal wires can detrimentally affect the performance of the whole computing system. This phenomenon is particularly enhanced when dealing with large crossbars. Several methods have been proposed to cope with this issue, but an exact analytical solution of the wire resistance effect has never been provided. This work gives a closed-form mathematical description of the wire resistance contribution when performing a matrix-vector multiplication. The chief contribution of the work is the possibility to understand the exact degradation of the system's accuracy due to the presence of wire resistance. In particular, this mathematical description permits to evaluate the influence of both vertical and horizontal interconnecting lines and enables the correct computation of the effective conductance matrix and the voltage drop. Future research activity plans include the combination of these results with the current approaches used to compensate the output deviation and the development of engineering/cad tools for designers to mitigate this critical systematic effect.