A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture

This paper presents a switched capacitor-based 3C multiplier for multibit (4-b) multiplication and accumulation (MAC) operation in analog compute-in-memory (CIM) architecture. The proposed multiplier works on the principle of sequential charge sharing between three capacitors. The proposed 3C multiplier has better area efficiency than state-of-the-art because it is independent from the input bit precision and for N-bit MAC operation, it requires only three capacitors. The proposed multibit MAC scheme achieves 1.12x improvement in Figure-of-Merit (FoM) for 4-b MAC operation than existing best state-of-the-art. The functionality of proposed MAC scheme is validated using post layout simulations in 65nm TSMC PDK.