Real-Time FPGA Investigation of Potential FEC Schemes for 800G-ZR/ZR+ Forward Error Correction

Forward error correction (FEC) performance down to 1e-15 bit error rate (BER) of a open FEC code (OFEC), which was recently proposed for the 800G inter-data center interconnect (DCI) standard, is verified with a 100-piece-FPGA implementation at a record 400-Gbps throughput. Besides the OFEC, we also investigate the cons and pros of the concatenated staircase and Hamming code (CFEC) and multilevel codes (MLC) of a concatenated Low-Density Parity-Check (LDPC) and Turbo Product Code (TPC), which are the candidate schemes for the 800G-ZR FEC. The OFEC performance as a function of decoding iterations of Soft-in Soft-out (SISO) and Hard-in Hard-out (HIHO) is investigated, and FPGA emulations reveal the existence of an error flare of the OFEC with two SISO iterations and an severe error floor with one HIHO iteration even with four SISO iterations. Further investigations on different combinations of SISO and HIHO iterations, revealed that three SISO and two HIHO iterations are the optimal choice. Based on this iteration configuration, we studied the methods that decreasing the test patterns (TP) of SISO decoder and the soft bits to reduce the implementation complexity. Then we proposed the simplified OFEC scheme for 800G-ZR application, providing 1.81e-2 pre-FEC BER threshold with half power dissipation of standard OFEC, achieving a trade-off between the error correction performance and power dissipation. Finally, we investigated the performance of performance enhanced OFEC with 24.3% overhead and 2.5e-2 pre-FEC threshold, and finally, FEC candidates for the 800G-ZR+ applications are studied, indicating that the OFEC and channel polarized multilevel coding (CP MLC) are the most promising schemes.