Hardware Implementation of Multi-kernel Function for Support Vector Machine Classification Using Stochastic Logic

The support vector machine (SVM) is a supervised learning method widely used for classification and regression in the machine learning. The nonlinear kernel functions in the SVM are involved in high hardware cost in practical implementations. This paper presents a general stochastic circuit architecture for various kernel functions with an aim to reducing hardware complexity. In the proposed stochastic circuits, the unipolar format is applied for implementing linear, polynomial, hypertangent and radial basis functions. The innovation of the presented design lies in the reduction on the total number of random number generators (RNGs) with the correlation technique. The synthesized results show that the circuit area of the proposed design is improved as compared to the previous finite state machine (FSM)-based method. Experimental results of Iris flower classification problem indicate that the accuracy with the RBF and hypertangent functions are improved by 60% and 10%, respectively, over the previous design as the length of the bit-stream is 2 ¹⁰ .