Low Temperature Material for 1st Level Interconnect in Semiconductor Packaging

The objective of this project was to determine whether low temperature materials (LTM) being used in other levels of electronics assembly could also be used for 1 st level interconnects in semiconductor packaging. LTM are materials that enable processing at temperatures lower than those required by more conventional lead-free systems such as SnAgCu (SAC) solder. Achievement of the objective was pursued using a multiprong approach. •Leverage the expertise of a diverse industry led team to identify challenges and requirements in key application sectors that might use LTM. These included high performance computing (HPC), Automotive, Aerospace & Defense, Mobile & Portable Devices, Sensors / Medical / Wearables / IoT and LED luminaries. •Review the compatibility of the LTM and the processes used in 2 ^nd level assembly with the special requirements of 1 ^st level packages •Conduct a literature survey to determine the current status of LTM within industry. •Administer a market survey to determine •the interest in lowering process temperatures in 1 ^st level assembly, •the extent of current usage of LTM and •the need and driving factors for LTM in 1 ^st level interconnections. The results of the survey indicate that while there is an interest in the potential benefits of lower temperature processes, usage of LTM is currently limited to a relatively small number of special cases and the LTM being used or planned for use were different from those being implemented at other levels of assembly. The review of the compatibility of currently available LTM identified various issues that would have to be addressed before their use could be extended to the 1st level. There were three approaches mentioned to incorporate these LTM: 1)Replace the interconnect materials completely with low temperature materials 2)Use traditional solders for attachment of certain items followed by second attachment steps using L TM for thermal sensitive elements (sequential hierarchical assembly) 3)Attach a component or die that has traditional SAC solder on it but has LTM on the substrate side (hybrid interconnect)